DECODER PENYANDIAN SALURAN HDB3 BERBASIS FPGA

Abstract

In digital communication systems, information is represented in the form of zero and one bit. For somedistance, this representation may be identified on the receiver. Conversely for long distance will cause dc componentproblems and synchronization. High Density Bipolar-3 zero (HDB3) encoding is one of the scrambling techniques thatadapt the Alternate Mark Inversion (AMI) encoding problem in the synchronization process for long zero bit sequences.In this study designed Decoder HDB3 line coding using FPGA with System on Chip (SoC) method. The results of thisstudy show that by adding non-zero insertion bits to long zero bit sequences, no longer form a straight line thatresembles noise. But like the actual display of bits but does not follow the AMI algorithm that makes each bit oneopposite the polarity. So it is easier to recovery the bits of information on the receiver.